Power/performance optimized memory controller considering processor power states

ABSTRACT

When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of computer systems,more particularly relating to methods and apparatuses for reducing powerconsumption in computer systems.

BACKGROUND

[0002] Computer systems are pervasive in the world, including everythingfrom small handheld electronic devices, such as personal data assistantsand cellular phones, to application-specific electronic devices, such asset-top boxes, digital cameras, and other consumer electronics, tomedium-sized mobile systems such as notebook, sub-notebook, and tabletcomputers, to desktop systems, workstations, and servers.

[0003] Over the last few years, there have been many advances insemiconductor technology that have resulted in the development ofimproved electronic devices having integrated circuits (IC) operating athigher frequencies and supporting additional and/or enhanced features.While these advances have enabled hardware manufacturers to design andbuild faster and more sophisticated computer systems, they have alsoimposed a disadvantage in higher power consumption, especially forbattery-powered computer systems.

[0004] A variety of techniques are known for reducing the powerconsumption in computer systems. For example, the Advanced Configurationand Power Interface (ACPI) Specification (Rev. 2.0a, Mar. 31, 2002) setsforth information about how to reduce the dynamic power consumption ofportable and other computer systems. With respect to processors used incomputer systems, four processor power consumption modes (C0, C1, C2,and C3) are defined in the ACPI Specification. For example, when theprocessor 105 is executing instructions, it is in the C0 mode. The C0mode is a high power consumption mode. When the processor 105 is notexecuting instructions or idle, it may be placed in one of the low powerconsumption modes C1, C2 or C3. An Operating System (OS) in the computersystem may dynamically transition the idle processor 105 into theappropriate low power consumption mode.

[0005] The C1 power mode is the processor power mode with the lowestlatency. The C2 power mode offers improved power savings over the C1power mode. In the C2 power mode, the processor is still able tomaintain the context of the system caches. The C3 power mode offersstill lower power consumption compared to the C1 and C2 power modes, buthas higher exit latency than the C2 and C1 power modes. In the C3 powermode, the processor 105 may not be able to maintain coherency of theprocessor caches with respect to other system activities.

[0006] While the reduced power consumption modes defined by the ACPISpecification and known techniques have many advantages, there is acontinuing need for ways to further reduce the power consumption ofcomputer systems, including power consumption of individual componentssuch as, for example, a display, a disk drive, an integrated graphicsprocessor, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following drawings disclose various embodiments of thepresent invention for purposes of illustration only and are not intendedto limit the scope of the invention.

[0008]FIG. 1 is a block diagram illustrating an example of a computersystem.

[0009]FIG. 2 is a block diagram illustrating an example of a chipset ina computer system, according to one embodiment.

[0010]FIG. 3 is a block diagram illustrating an example of a graphicscontroller, according to one embodiment.

[0011]FIG. 4 is a flow diagram illustrating an example of a process usedfor reducing the power consumption of the memory and the graphicscontroller, according to one embodiment.

[0012]FIG. 5 is a flow diagram illustrating a process for restoring thememory and the graphics controller to a normal power mode, according toone embodiment.

DETAILED DESCRIPTION

[0013] Methods and systems are disclosed for controlling powerconsumption of computer systems. For one embodiment, when a processor ofa computer system is in a low power mode, power consumption of one ormore components of a memory coupled to the processor and of other systemcomponents that have controllers associated with making requests to thememory may be reduced.

[0014] In the following description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the present invention. It will be evident, however, toone skilled in the art that the present invention may be practicedwithout these specific details. In other instances, well-knownstructures, processes and devices are presented in terms of blockdiagrams and flowcharts to illustrate embodiments of the invention, andthey may not be discussed in detail to avoid unnecessarily obscuring theunderstanding of this description.

[0015] As used herein, the term “when” may be used to indicate thetemporal nature of an event. For example, the phrase “event ‘A’ occurswhen event ‘B’ occurs” is to be interpreted to mean that event A mayoccur before, during, or after the occurrence of event B, but isnonetheless associated with the occurrence of event B. For example,event A occurs when event B occurs if event A occurs in response to theoccurrence of event B or in response to a signal indicating that event Bhas occurred, is occurring, or will occur.

[0016]FIG. 1 is a block diagram illustrating an example of a computersystem. The computer system 100 may include a central processing unit(CPU) or processor 105 and a system memory 115 that is coupled with theprocessor 105 via bus 15. The computer system 100 may include a displayunit 124 (e.g., a liquid crystal display (LCD) or a cathode ray tube(CTR)). Data (e.g., text, graphics, etc.) displayed on the display unit124 may be controlled by a graphics controller residing in a chipset(not shown). The computer system 100 may further include an alphanumericinput device 20 (e.g., a keyboard), a cursor control device 25 (e.g., amouse) and a disk drive unit 30.

[0017] The disk drive unit 30 may include a machine-readable medium (notshown) on which is stored a set of instructions (e.g., softwareapplication) embodying any one, or all, of the embodiments describedherein. The instructions may also reside, completely or at leastpartially, within the main memory 115 and/or within the processor 105.The instructions may furthermore be transmitted or received via thenetwork interface device 35. The computer system 100 may also include anetwork interface 35 to connect to one or more networks. The computersystem 100 may be powered by an alternating current (AC) power source orby a direct current (DC) power source using one or more batteries.

[0018] Although not shown, the bus 15 may include one or more of addressbus, bus control signals and data bus and/or even a memory controllerthat arbitrates between all memory access requests. The processor 105may control the bus 15 which means communications between input/output(I/O) devices (or slave devices) need involvement of the processor 105.Although not shown, there may be other controllers in the computersystem 100 that are capable of taking turns with the processor 105 atmaking access requests to the memory 115. This may allow a controller todrive the address bus and the control signals of the bus 15 with minimalintervention by the processor 105. For example, the processor 105 may bebusy performing other tasks that do not require the bus 15, or theprocessor 105 may be idle in a low power state. A controller may containits own processor or microcontroller or engine that generates requeststo the memory 115. A controller may be, for example, an Ethernetcontroller, a sound transducer controller, a universal serial bus (USB)controller, a graphics controller, etc.

[0019] In the following description, for purposes of explanation, anintegrated graphics controller may be used as an example of a controllerthat is capable of controlling the bus 15 and accessing the memory 115with minimal intervention by the processor 105. One skilled in the artwill recognize that the description may also be applicable to othercontrollers.

[0020]FIG. 2 is a block diagram illustrating an example of a chipset ina computer system, according to one embodiment. The computer system 100may include a central processor 105 and a chipset 200. The computersystem 100 may also include a memory 115. The chipset 200 may be anintegrated graphics chipset. The chipset 200 may, for example, be theIntel 845G integrated graphics chipset from Intel Corporation of SantaClara, Calif. The chipset 200 may include an integrated graphicscontroller 212 to provide graphics/video support. The chipset 200 mayalso include a graphics interface 222 (e.g., Accelerated Graphics Port(AGP) interface) to support external graphics controllers (not shown)for advanced graphics capability. An external graphics controller mayhave own local memory.

[0021] The chipset 200 may also include a memory controller 213 thatinterfaces with the memory 115 to satisfy read/write requests from theprocessor 105. The memory 115 may be, for example, dynamic random accessmemory (DRAM), synchronous dynamic random access memory (SDRAM), doubledata rate (DDR) SDRAM, etc. The chipset 200 may also include an I/Ocontroller 214 to interface with peripheral devices (not shown).Although FIG. 2 illustrates the processor 105 as a different module fromthe graphics controller 212, one or more of the processor 105, thegraphics controller 212, and the I/O controller 214 may be implementedin one module or in multiple modules. For example, functionalities ofthe memory controller 213 may be integrated in the processor 105.

[0022] The graphics controller 212 and the memory 115 may receivereference clock signals from a clock generator 205. The graphicscontroller 212, the memory controller 213 and the memory 115 may alsoinclude delayed locked loop (DLL) circuit(s) (not shown) used, forexample, to control timings, etc.

[0023] The graphics controller 212 may perform computations to getdisplay data from the memory 115 and to output the display data to thedisplay unit 124 via the video out port 220. The graphics controller 212may also control other operational behaviors of the display unit 124including, for example, refresh rates, backlight brightness and thelike. The activities performed by the graphics controller 212 maycontribute to the power consumed by the chipset 200 and by the system100.

[0024]FIG. 3 is a block diagram illustrating an example of a graphicscontroller, according to one embodiment. The graphics controller 212 mayinclude a display buffer 310 to store the display data. The displaybuffer 310 may be associated with a display streamer (DS) 305 that maybe used to determine when to request the display data from the memory115. The display buffer 310 may be a first-in first-out (FIFO) buffer.The display data may be fed from the display buffer 310 to a displayengine 315. Although the example illustrated in FIG. 3 refers to the DS305 as a separate component, it may be possible that the DS 305 and itsfunctionalities may be incorporated elsewhere such as, for example, inthe memory controller 300 of the graphics controller 212.

[0025] It may be noted that the graphics controller 212 and the memorycontroller 213 (illustrated in FIG. 2) (and thus the processor 105) mayshare the memory 115. That is, the graphics controller 212 may have itsown memory controller 300 to initiate own accesses to the memory 115without direct control of the processor 105. For example, considering aunified memory architecture (UMA) chipset with integrated graphicscontroller, in this case the memory controller 213 and the graphicscontroller 212 in the chipset 200 share the same memory 115, and thepower consumption of the graphics controller 212 and the memory 115 maybe reduced. When there is an external graphics controller (not shown)that has own local memory, the power consumption of the chipset 200, thememory 115, and the external graphics controller and its local memorymay be reduced.

[0026] The memory 115 may be more efficient when it can provide thedisplay data at a high rate. The display data, however, may only beprocessed by the display engine 315 at a lower rate. Breaks orinterruptions in feeding the display data from the display buffer 310 tothe display engine 315 may result in visual artifacts such as, forexample, flickers or breaks in the final output on the display unit 124.As such, control values may need to be used. For example, the DS 305 mayuse a different set of control values for each display mode supported bythe graphics controller 212. A display mode may include, for example, acombination of display device resolution, color depth or pixel depth,refresh rates, and system configuration.

[0027] The control values may allow the DS 305 to determine when toretrieve the display data and how much of the display data to retrievefrom the memory 115. For example, the control values may include awatermark value and a burst length value. The watermark value mayrepresent a value that falls between a minimum buffer value and amaximum buffer value, depending on the size of the buffer 310. The burstlength value may represent the amount of display data that the DS 305may request from the memory 115 at a time for a particular display mode.The DS 305 may use the watermark value and the burst length value tomore efficiently control how and when the display data is fetched fromthe memory 115 and presented to the display engine 315 to display on thedisplay unit 124. This may help eliminating visual artifacts or displaycorruption seen on the display unit 124.

[0028] The display buffer 310 may store up to a certain number ofdisplay data fetched from the memory 115. When the amount of displaydata in the display buffer 310 drops below the watermark value for thecurrent display mode, the DS 305 requests more display data from thememory 115. It may be noted that other techniques other than using thewater mark value and the burst length value to control when and how muchdisplay data to retrieve from the memory 115 may also be used.

[0029] The processor 105 illustrated in FIG. 2 may dynamically computethe watermark values and burst length values for different display modesthat may result from different configurations of the computer system100. A configuration may be, e.g., a particular combination of multipledisplays, display resolutions, color depths, refresh rates, overlayscaling conditions, video capture conditions, and/or other systemconfigurations. The processor 105 may program one of the watermarkvalues as a current watermark value and one of the burst length valuesas a current burst length value into the graphics controller 212 for usein processing the display data to be displayed on the display unit 124.

[0030] During normal operation, the memory 115 may be in a memoryrefresh mode and its contents may be refreshed or recharged at everymemory refresh interval, for example. For one embodiment, the memory 115may include features that enable its components to refresh on their own(or self-refresh), independent from the processor 105 or externalrefresh circuits (not shown).

[0031] According to the ACPI Specification, when the processor 105 isnot executing instructions, the power consumption by the computer system100 may be reduced by placing the processor 105 in a low power mode suchas, for example, the C3 power mode (or C2 or C1 power mode). When theprocessor 105 is in the low power mode (e.g., the C3 mode), the DS 305may still need to fetch the display data from the memory 115 for displayrefresh based on the control values (e.g., the watermark value and theburst length value). This may occur when other controller may or may notdesire to access memory 115. When all the controller devices'contributions to memory access latency can be taken into account, thetechniques described herein may work when the processor 105 is in the C3power mode or in the C2 power mode or also in the C1 power mode.

[0032] For one embodiment, when the processor 105 is in the low powermode, the memory 115 may also be placed in a low power mode. That is,power consumption of one or more components of the memory 115 may bereduced. This may have minimal effect on processor performance. Forexample, the power consumption of the memory 115 may be reduced byplacing the memory 115 in a self-refresh mode. Self-refresh may be adynamic random access memory (DRAM) power reduced state where the memoryrequires no input clock and attempts to only have power consumptionrequired to keep its memory states. This may be done, for example, byissuing a self-refresh command to the memory 115. Placing the memory 115into the self-refresh mode may enable its contents to be saved whilereducing power consumption.

[0033] One skilled in the art may recognize that other techniques mayalso be used to place the memory 115 into the low power mode such as,for example, by placing the memory 115 in a pre-charge power-down oractive power-down. Precharge power down is a DRAM power reduced statethat still requires system clocking, and that all DRAM memory pages areclosed before it can be entered. Active power down is a DRAM powerreduced state that requires system clocking, but not all DRAM pages areclosed before it can be entered. Generally, the lower power states mayhave longer powerup or wakeup latency times.

[0034] For one embodiment, when the processor 105 is placed into the lowpower mode, the power consumption of the memory 115 may be reduced byreducing power to a delay locked loop (DLL) circuit associated with thememory 115.

[0035] For one embodiment, when the power consumption of the memory 115is reduced, the power consumption of one or more components of thegraphics controller 212 may also be reduced. The one or more componentsof the graphics controller 212 may include components that are needed torun the memory 115. This may place the graphics controller 212 in a lowpower mode and may have minimal effect on processor performance. Forexample, this may include reducing power (such as shutting off the DLL)to a delay locked loop (DLL) circuit associated with the graphicscontroller 212, or shutting off the clocking to the memory from thegraphics controller 212. Reducing power consumption as used herein mayinclude powering off or reducing power from a current amount to a loweramount when applicable.

[0036] In order to reduce the overall power consumption of the computersystem 100 as much as possible, it may be advantageous for the memory115 and the graphics controller 212 to stay in the low power mode for aslong as possible. Of course, at some point, waking up the memory 115 andthe graphics controller 212 may be necessary to allow the computersystem 100 to operate in an acceptable manner. For example, at somepoint the amount of display data in the display buffer 310 may bereduced to the watermark level and a memory burst is required. In thissituation, it may be necessary to wake up the graphics controller 212and the memory 115 and restore them to their normal power mode. Wakingup as used herein may include powering on or increasing power from a lowamount to a higher amount when applicable.

[0037] As described above, the watermark value may be used to determinewhen a memory burst is necessary, and the burst length value may be usedto determine the amount of data to be fetched from the memory 115 eachtime. Typically, during normal processor power mode (e.g., C0 powermode), the memory bursts may be smaller and spaced closer in time. Thus,when the processor is in a low power mode (e.g., C1/C2/or C3), it may beadvantageous to change the control values (e.g., the burst length valueand the water mark value) so that the memory bursts may be longer andspaced further apart in time. Of course, this may depend on the currentdisplay mode and the size of the display buffer 310. Changing thecontrol values may allow the wakeup latency time to be shorter than thetime to process the display data in the display buffer 310. The wakeuplatency time may include time to restore power to the one or morecomponents of the memory 115 and of the graphics controller 212.

[0038]FIG. 4 is a flow diagram illustrating an example of a process usedfor reducing the power consumption of the memory and the graphicscontroller, according to one embodiment. At block 400, the processor 105is placed in a low power mode. As described above, there may be wakeuplatency associated with restoring the memory 115 to a normal power modefrom a low power mode. It may be possible that when the processor 105 isplaced in the low power mode, the buffer 310 may be partially populatedwith existing display data such that the wakeup latency time may betemporarily longer than the time to process the existing display data inthe display buffer 310.

[0039] At a next memory burst, the display buffer 310 may be populatedwith more display data (e.g., as dictated by the burst length value),and the wakeup latency time may be shorter than the time it takes toprocess the display data now in the display buffer 310. This may allowthe memory 115 to be in the low power mode for a longer time.

[0040] At block 405, the power consumption of one or more components ofthe memory 115 is reduced. Reducing the power consumption of one or morecomponents of the memory 115 may include, for example, placing thememory 115 in a self-refresh mode. When the memory 115 is in aself-refresh mode, power to the DLL circuit associated with the memory115 may be reduced.

[0041] At block 410, the power consumption of one or more components ofthe graphics controller 212 is reduced. This may include, for example,shutting down the clocks to memory and reducing the power consumption ofthe DLL circuit associated with the graphics controller.

[0042]FIG. 5 is a flow diagram illustrating a process for restoring thememory and the graphics controller to a normal power mode, according toone embodiment. At block 505, the graphics controller 212 is in a lowpower mode. At block 510, a test is performed to determine if thegraphics controller 212 needs to exit the low power mode. For example,the test may verify if the watermark level has or has not been reached.The test may be performed so that the graphics controller 212 can exitthe low power mode at an appropriate time before the powerup latencytime is going to be longer than the already buffered display data cansupport. If the graphics controller 212 does not need to exit the lowpower mode, the process stays at block 510. Otherwise, the process flowsto block 515.

[0043] At block 515, the power to the memory 115 is restored to thenormal power mode. This may include, for example, taking the memory 115out of the self-refresh mode and powering up the DLL circuit associatedwith the memory 115. At block 520, the power to the graphics controller212 is restored to the normal power mode. This may include, for example,powering up the DLL circuit associated with the graphics controller 212.It may be noted that the graphics controller 212 may drift in and out ofthe low power mode. For example, the graphics controller 212 may be outof the low power mode when more display data is needed and a memoryburst is to be performed, as shown in block 525.

[0044] When the control values (e.g., the burst length value and thewatermark value) are used and they are changed to increase the time thatthe memory 115 and the graphics controller 212 stay in the low powermode, these control values may need to be restored to their originalvalues normally used when the processor 105 is in the normal power mode.Note that it may be necessary to wait for the memory 115 and thegraphics controller 212 to power up before taking the processor 105 outof the low power mode.

[0045] It may be noted that although the processes described in FIG. 4and in FIG. 5 refer to the graphics controller 212, one skilled in theart will recognize that those processes may also be applicable to othercontroller devices that are capable of accessing the memory 115independently of the processor 105. It may also be noted that althoughthe techniques described above refer to display data, one skilled in theart will recognize that the techniques may also be used with any dataincluding, for example, time critical data.

[0046] Techniques for reducing power consumption in computer systemshave been disclosed. The power consumption of a computer system may bereduced when the processor is in a low power mode by reducing the powerconsumption of the memory and of a bus controller associated with thememory. Although the techniques described above refer generally to thegraphics controller and the processor sharing the same memory, when thegraphics controller has its own local memory, power consumption of thegraphics controller may be managed using the same technique. Inaddition, although the techniques described above refer to reducing thepower consumption of the DLL circuits of the memory 115 and of thegraphics controller 212, the techniques may also be used to reduce powerconsumption of other components in the computer system 100.

[0047] Although the present invention has been described with referenceto specific exemplary embodiments, it will be evident that variousmodifications and changes may be made to these embodiments withoutdeparting from the broader spirit and scope of the invention as setforth in the claims. Accordingly, the specification and drawings are tobe regarded in an illustrative rather than a restrictive sense.

What is claimed is:
 1. A method, comprising: when a processor is placedin a low power mode, reducing power consumption of one or morecomponents of a memory coupled to the processor and of one or morecomponents of a controller device needed to run the memory.
 2. Themethod of claim 1, wherein reducing the power consumption of the one ormore components of the memory includes placing the memory in aself-refresh mode.
 3. The method of claim 1, wherein reducing the powerconsumption of the one or more components of the memory includes placingthe memory in a precharge powerdown mode or an active powerdown mode. 4.The method of claim 2, wherein reducing the power consumption of one ormore components of the controller device needed to run the memoryincludes reducing power consumption of a delay locked loop (DLL) circuitassociated with the controller device.
 5. The method of claim 4, whereinreducing the power consumption of one or more components of thecontroller device needed to run the memory further includes reducingpower of control signals and clocks associated with the controllerdevice.
 6. The method of claim 1, wherein the controller device and theprocessor share the memory.
 7. The method of claim 1, wherein thecontroller device is a graphics controller.
 8. The method of claim 7,wherein an amount of display data to be retrieved from the memory isdetermined based on a wakeup latency time associated with the memory andthe graphics controller.
 9. The method of claim 8, wherein time toprocess the display data retrieved from the memory is at least equal tothe wakeup latency time.
 10. The method of claim 1, further comprising:verifying that the controller device needs to exit a low power modebefore increasing the power consumption of the one or more components ofthe controller device
 11. A method, comprising: performing a firstmemory burst to retrieve display data from a memory, the memory coupledto a graphics controller; reducing power of one or more components ofthe memory and one or more components of the graphics controller thatare needed to run the memory; sending the display data to a displaycoupled to the graphics controller; and restoring the power of the oneor more components of the memory and the one or more components of thegraphics controller to perform a subsequent memory burst as they becomenecessary.
 12. The method of claim 11, wherein the power of the one ormore components of the memory and the one or more components of thegraphics controller is reduced when a processor coupled to the memory isin a low power mode.
 13. The method of claim 12, wherein the power ofthe one or more components of the memory and the one or more componentsof the graphics controller is restored when the processor is in the lowpower mode.
 14. The method of claim 13, wherein the processor and thegraphics controller share the memory.
 15. The method of claim 11,wherein reducing the power of the one or more components of the memorycomprises placing the memory in a self-refresh mode, a prechargepowerdown mode, or an active powerdown mode.
 16. The method of claim 15,wherein placing the memory in a self-refresh mode includes reducingpower consumption of a delay locked loop (DLL) circuit associated withthe memory.
 17. The method of claim 11, wherein reducing the power ofthe one or more components of the graphics controller comprises reducingthe power of a delay locked loop (DLL) circuit associated with thegraphics controller.
 18. The method of claim 17, wherein reducing thepower of the one or more components of the graphics controller furthercomprises reducing the power of control signals and clocks associatedwith the graphics controller.
 19. A computer readable medium comprisingexecutable instructions which, when executed in a processing system,causes the processing system to perform a method, comprising: when aprocessor is placed in a low power mode, reducing power consumption ofone or more components of a memory coupled to the processor and of oneor more components of a controller device associated with the memory.20. The computer readable medium of claim 19, wherein reducing the powerconsumption of the one or more components of the memory includes placingthe memory in a self-refresh mode, a precharge powerdown mode, or anactive powerdown mode.
 21. The computer readable medium of claim 20,wherein placing the memory in a self-refresh mode includes reducingpower consumption of a delay locked loop (DLL) circuit associated withthe memory.
 22. The computer readable medium of claim 21, whereinreducing the power consumption of one or more components of thecontroller device includes reducing power consumption of a delay lockedloop (DLL) circuit associated with the controller device.
 23. Thecomputer readable medium of claim 22, wherein reducing the power of theone or more components of the controller device further includesreducing the power of control signals and clocks associated with thecontroller device.
 24. The computer readable medium of claim 19, whereinthe controller device and the processor share the memory.
 25. Thecomputer readable medium of claim 24, wherein the controller device is agraphics controller.
 26. The computer readable medium of claim 25,wherein an amount of display data to be retrieved from the memory isdetermined based on a wakeup latency time associated with the memory andthe graphics controller.
 27. The computer readable medium of claim 26,wherein time to process the amount of display data retrieved from thememory is at least equal to the wakeup latency time.
 28. The computerreadable medium of claim 19, wherein the one or more components of thecontroller device includes components needed to run the memory.
 29. Thecomputer readable medium of claim 28, further comprising: verifying thatthe controller device needs to exit a low power mode before subsequentlyrestoring the power consumption of the one or more components of thecontroller device.
 30. A system comprising: a processor; a memorycoupled to the processor; and a controller device coupled to theprocessor and to the memory, wherein the controller device and theprocessor share the memory, and wherein power consumption of one or morecomponents of the memory and of one or more components of the controllerdevice is reduced when the processor is in a low power mode.
 31. Thesystem of claim 30, wherein the one or more components of the memoryincludes a delay locked loop (DLL) circuit associated with the memory.32. The system of claim 30, wherein the one or more components of thecontroller device includes a delay locked loop (DLL) circuit associatedwith the controller device.
 33. The system of claim 30, wherein thepower consumption of the one or more components of the memory is reducedby placing the memory in a self-refresh mode.
 34. The system of claim30, wherein the power consumption of the memory and of the controllerdevice is subsequently increased when it is necessary to retrieve datafrom the memory.
 35. The system of claim 30, wherein the one or morecomponents of the controller device are needed to run the memory.
 36. Asystem comprising: a processor; a memory coupled to the processor; acontroller device coupled to the memory, wherein when the processor isin a low power mode, power consumption of one or more components of thecontroller device that are needed to run the memory is reduced.
 37. Thesystem of claim 36, wherein the power consumption of one or morecomponents of the memory is also reduced when the processor is in thelow power mode.
 38. The system of claim 37, wherein the one or morecomponents of the memory includes a delay locked loop (DLL) circuitassociated with the memory.
 39. The system of claim 37, wherein thepower consumption of the one or more components of the memory is reducedby placing the memory in a self-refresh mode, a precharge powerdownmode, or an active powerdown mode.
 40. The system of claim 36, whereinthe one or more components of the controller device includes a delaylocked loop (DLL) circuit associated with the controller device.
 41. Thesystem of claim 37, further comprising a buffer coupled to thecontroller device, the buffer is to store data retrieved from the memoryusing the controller device.
 42. The system of claim 41, wherein thedata is retrieved from the memory at a first time when the processor isin the low power mode.
 43. The system of claim 42, wherein the powerconsumption of the one or more components of the memory and of thecontroller device is increased when it is necessary to retrieve the datafrom the memory at a subsequent time while the processor is in the lowpower mode.